1076.6-1999 IEEE Standard for VHDL Register Transfer Level by PDF

ISBN-10: 0738118192

ISBN-13: 9780738118192

A typical syntax and semantics for VHDL check in move point (RTL) synthesis is outlined. The subset of IEEE 1076 (VHDL) that's compatible for RTL synthesis is outlined, besides the semantics of that subset for the synthesis area.

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Additional info for 1076.6-1999 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis

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Type conversions on a formal port shall not be supported. 1 Instantiation of a component Component instantiation shall be supported. 7 Generate statement generate_statement ::= generate_label: generation_scheme generate [ { block_declarative_item } begin ] { concurrent_statement } end generate [generate_label] ; generation_scheme ::= for generate_parameter_specification | if condition label ::= identifier Supported: — — — Generate_statement Generate_scheme Label Not supported: — — Block_declarative_item (the declarative region) Reserved word begin The generate parameter specification shall be statically computable and of the form “identifier in range” only.

5 The context of overloaded resolution The context of overloaded resolution shall be supported. 2 Design libraries library_clause ::= library logical_name_list ; logical_name_list ::= logical_name {, logical_name} logical_name ::= identifier Copyright © 2000 IEEE. All rights reserved. 4 Order of analysis The order of analysis shall be supported. 12 Elaboration No constraints shall be put on elaboration for synthesis. 13 Lexical elements Real literals are only allowed in after clauses. Extended identifiers shall not be supported.

NOTES 1—If the type of the case expression includes metalogical values, and if not all the metalogical values are included among the case choices, then the case statement must include an others choice to cover the missing metalogical choice values (see IEEE Std 1076-1993). 3-1997). 9 Loop statement loop_statement ::= [ loop_label: ] [ iteration_scheme ] loop sequence_of_statements end loop [ loop_label ] ; iteration_scheme ::= while condition | for loop_parameter_specification parameter_specification ::= identifier in discrete_range discrete_range ::= discrete_subtype_indication | range Copyright © 2000 IEEE.

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1076.6-1999 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis


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